Turning to FIG. 1, an example of a conventional latched comparator 100 can be seen. This latched comparator 100 generally comprises a pre-amplifier 104, latch 106, inductors L1 and L2, and resistors R1 and R2. The pre-amplifier 104 generally comprises a pair of differential input transistors Q3 and Q4 (which can be NMOS transistors), isolation transistors Q1 and Q2 (which can be NMOS transistors), and a bias transistor Q5 (which can be an NMOS transistor). The latch 106 generally comprises cross-coupled transistors Q6 and Q7 (which can be NMOS transistors) and a switching transistor Q8 (which can be an NMOS transistors).
In operation, the latched comparator 100 tracks the differential input signals INP and INM of the pre-amplifier 104 during a track phase of a latch signal LATCH and holds or latches the differential output signals OUTP and OUTM of the pre-amplifier 104 during a hold phase of a latch signal LATCH. Namely, the pre-amplifier 104 amplifies the difference between the differential input signals INP and INM to generate the differential output signal OUTP and OUPM (where the difference between signals OUTP and OUTM tracks the difference between signals INP and INM). These differential output signals OUTP and OUTM are provided to load 102 (which can be capacitive and which is represented, for example, by capacitors CL). When the latch signal LATCH becomes logic high or “1”, switching transistor Q8 activates latch 106 so that the pair of cross-coupled transistors Q6 and Q7 can hold or latch the differential output signals OUTP and OUTM of pre-amplifier 104. To improve the track bandwidth and to improve the latch time during regeneration, inductors L1 and L2 are provided, which generally provide shunt peaking in the tracking phase (i.e., when the latch signal LATCH is logic low or “0”). A problem with this configuration, however, is that the latch 106 sees or is directly exposed to load capacitances (i.e., capacitors CL).
Latched comparator 200 of FIG. 2, on the other hand, attempts to solve this problem by introducing resistors R3 and R4 between the output terminals of the pre-amplifier 104 and the latch 106. These resistors R3 and R4 generally isolate the latch 106 from load capacitances (i.e., capacitors CL), but there is a voltage drop that occurs as a result of the inclusion of resistors R3 and R4. Namely, resistors R3 and R4 reduce the voltage swing from latch 106 (i.e., the difference between voltages VLM and VLP) to the output terminals of pre-amplifier 104 (i.e., difference between signals OUTP and OUTM, which are generally voltages).
Therefore, there is a need for a latched comparator with improved performance.
Some other conventional circuits are: U.S. Patent Pre-Grant Publ. 2009/0021283; Japanese Patent Publ. No. JP03-145330; Park et al., “Design Techniques for high Performance CMOS Flash Analog-to-Digital Converters,” Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005, Vol. 1, pgs. 131-134, Oct. 31, 2005; Park et al., “A 3.5GS/s 5-b Flash ADC in 90 nm CMOS,” IEEE 2006 Custom Integrated Circuits Conference (CICC), pgs. 489-492; and Park et al., “A 4GS/s 4-b Flash ADC in 0.18-μm CMOS,” IEEE J. of Solid-State Circuits, Vol. 42, No. 9, pgs. 1865-1872, September 2007.